The present invention relates to semiconductor integrated circuits, and more particularly, to Large Scale Integrated (LSI) circuits comprising a plurality of mutually connected unit cells on a single semiconductor chip. The invention also includes an improved method for fabricating the improved semiconductor devices.
A semiconductor integrated circuit consists of functional circuits integrally formed on a single semiconductor substrate, so that circuit means using integrated circuits are characterized by their miniaturized dimensions and a remarkably high reliability in operation. Accordingly, the semiconductor integrated circuits are extremely valuable in numerous applications and fields. For example, in data processing systems wherein the object is to process data, or information, with accuracy as well as at a high speed. Thus, most of the circuits and specifically logic circuits or the like, in use are in the form of integrated circuits. In the art of semiconductor devices, dedicated and intense efforts have been made, and continue to be made, to increase the density of integration of circuit components formed on a single semiconductor substrate, or chip. With the progress of integrated circuit manufacturing techniques these efforts have resulted in a far more extensive function being performed by a single integrated circuit chip. Herein the term "cell" or "unit cell" is used to designate a fundamental functional circuit (semiconductor structure) which is employed to construct a more extensive circuit, subsystem or system. For example, the unit cell may be an AND circuit, a NAND circuit, an OR circuit, Flip-Flop circuit or the like. The term "LSI circuit" is used to designate a circuit including a plurality (sizeable number) of interconnected unit cells formed on a single semiconductor substrate, or chip. The term "LSI circuit" is also used to designate a much greater number of integrated circuit components as compared with a unit cell.
Conceptionally, the LSI circuit may be considered a development or extension of the conventional integrated circuit. However, practically, since in the LSI circuit a very sizeable number of circuit components must be contained on one substrate, a number of complications, in particular, cell size, cell content, cell configuration, wiring (interconnections) etc., must be carefully and fully addressed. These complications and problems, and in particular, wiring (interconnections) are not nearly so serious or acute, and are more readily solved at this time in the fabrication of conventional integrated circuits. In the fabrication of conventional integrated circuits the custom design approach, or techniques, have been very effective. (Where the custom design approach, or technique, as is well known in the art, may be defined as the maximum utility of the area of the semiconductor substrate, or chip, for only a portion of the circuits implemented on a particular substrate, or chip, by individually designing the component location and metallization connection for each required circuit). The custom design approach has been and is effective in the fabrication of conventional integrated circuits. The custom design approach usually results in an overall less dense substrate, or chip, due to less dense wiring between densely designed groups of circuits. Also the custom design approach requires a very sizeable amount of time and effort to design a particular system or subsystem. The custom approach is not practical in the fabrication of many large scale integrated (LSI) semiconductor devices where the circuit density is very high, the system circuit is complicated, and extensive, dense, complicated wiring is required. One of the strongest reasons the custom design approach is not particularly suited or efficient for LSI semiconductor devices is that the custom design approach necessitates designing, for each individual LSI circuit (or part number) both impurity diffusion masks for forming the circuit elements and interconnection masks for interconnecting the circuit elements.
In order to obviate the deficiencies in the custom design approach a number of approaches have been proposed and utilized in the art. One such approach is the masterslice design approach. In the master-slice design approach, a great number of circuit elements or unit cells are formed and arranged on a substrate beforehand so as to be able to obtain by modifying the interconnection metallization patterns a number of different LSI circuits (LSI semiconductor devices or part numbers). It will be apparent, as known in the art, that any one of a number of desired LSI circuits may be fabricated by properly interconnecting the already formed and arranged circuit elements, or cells. The masterslice design approach is advantageous in that the same diffusion mask (or masks) can be used to produce a plurality of different LSI circuits (LSI semiconductor devices or part numbers) merely by designing appropriate masks for effecting metallization for each part number or different LSI circuit. Providing interconnection metallization is the final fabrication step or steps in the process of producing LSI semiconductor devices. As stated earlier herein, the custom design approach and masterslice design approach for providing LSI semiconductor devices are respectively well known to persons skilled in the art.
With reference to U.S. Patent numbers, additional prior art disclosures and teachings in the field of integrated circuits are identified.
Reference is made to U.S. Pat. No. 3,312,871, entitled "Interconnection Arrangement for Integrated Circuits" granted Apr. 4, 1967 to H. Seki et al., and of common assignee herewith.
Reference is made to U.S. Pat. No. 3,377,513, entitled "Integrated Circuit Diode Matrix" granted Apr. 9, 1968 to R. M. Ashby et al.
Reference is made to U.S. Pat. No. 3,423,822 entitled "Method of Making Large Scale Integrated Circuit" granted Jan. 28, 1969 to I. A. Davidson et al.
Reference is made to U.S. Pat. No. 3,475,621 entitled "Standarized High Density Integrated Circuit Arrangement and Method" granted Oct. 28, 1969 to A. Weinberger and of common assignee herewith.
Reference is made to U.S. Pat. No. 3,484,932 entitled "Method of Making Integrated Circuits" (original filing date Aug. 31, 1962) granted Dec. 23, 1969 to C. R. Cook, Jr.
Reference is made to U.S. Pat. No. 3,553,830 entitled "Method For Making Integrated Circuit Apparatus" granted Jan. 12, 1971 to F. J. Jenny et al. and of common assignee herewith.
Reference is made to U.S. Pat. No. 3,558,992 entitled "Integrated Circuit Having Bonding Pads Over Unused Active Area Components" granted Jan. 26, 1971.
Reference is made to U.S. Pat. No. 3,581,385 entitled "Method For Fabricating Large Scale Integrated Circuits with Discretionary Wiring" granted June 1, 1971 to J. W. Lathrop.
Reference is made to U.S. Pat. No. 3,598,604 entitled "Process of Producing An Array of Integrated Circuits on Semiconductor Substrate" granted Aug. 10, 1971 to A. H. DePuy and of common assignee herewith.
Reference is made to U.S. Pat. No. 3,615,463 entitled "Process of Producing An Array of Integrated Circuits on Semiconductor Substrate" granted Oct. 26, 1971 to W. N. Kuscheel and of common assignee herewith.
Reference is made to U.S. Pat. No. 3,618,201 entitled "Method of Fabricating LSI Circuits" granted Nov. 9, 1971 to T. Makimoto et al.
Reference is made to U.S. Pat. No. 3,689,803 entitled "Integrated Circuit Structure Having A Unique Surface Metallization Layout" granted Sept. 5, 1972 to T. H. Baker et al and of common assignee herewith.
Reference is made to U.S. Pat. No. 3,702,025 entitled "Discretionary Interconnection Process" granted Nov. 7, 1972 to A. I. Archer.
Reference is made to U.S. Pat. No. 3,707,036 entitled "Method for Fabricating Semiconductor LSI Circuit Devices" granted Dec. 26, 1972 to T. Okabe et al.
Reference is made to U.S. Pat. No. 3,762,037, entitled "Method of Testing for the Operability of Integrated Semiconductor Circuits having A Plurality of Separable Circuits" granted Oct. 2, 1973 to T. H. Baker et al.
Reference is made to U.S. Pat. No. 3,771,217 entitled "Integrated Circuit Arrays Utilizing Discretionary Wiring and Method of Fabricating Same" granted Nov. 13, 1973 to T. E. Hartman.
Reference is made to U.S. Pat. No. 3,795,972 entitled "Integrated Circuit Interconnections by Pad Relocation" granted Mar. 12, 1974 to D. F. Calhoun.
Reference is made to U.S. Pat. No. 3,795,973 entitled "Multi-Level Large Scale Integrated Circuit Array Having Standard Test Points" granted Mar. 12, 1974 to D. F. Calhoun.
Reference is made to U.S. Pat. No. 3,795,974 entitled "Repairable Multi-Level Large Scale Integrated Circuit" granted Mar. 12, 1974 to D. F. Calhoun.
Reference is made to U.S. Pat. No. 3,795,975, entitled "Multi-Level Large Scale Complex integrated Circuit Having Functional Interconnected Circuit Routed to Master Patterns" granted Mar. 12, 1974 to D. F. Calhoun.
Reference is made to U.S. Pat. No. 3,981,070 entitled "LSI Chip Construction and Method" granted Sept. 21, 1976 to F. K. Buelow et al.
Reference is made to U.S. Pat. No. 3,983,619 entitled "Large Scale Integrated Circuit Array of Unit Cells and Method of Manufacturing Same" granted Oct. 5, 1976 to M. Kubo et al.
Reference is made to U.S. Pat. No. 3,984,860 entitled "Multi-Function LSI Wafers" granted Oct. 5, 1976 to J. C. Logue and of common assignee herewith.
Reference is made to U.S. Pat. No. 3,993,934 entitled "Integrated Circuit Structure Having a Plurality of Separable Circuits" granted Nov. 23, 1976 to T. H. Baker et al. and of common assignee herewith.
Reference is made to U.S. Pat. No. 3,999,214 entitled "Wireable Planar Integrated Circuit Chip Structure" granted Dec. 21, 1976 to E. E. Cass and of common assignee herewith.
Reference is made to U.S. Pat. No. 4,006,492 entitled "High Density Semiconductor Chip Organization" granted Feb. 1, 1977 to E. B. Eichelberger et al and of common assignee herewith.
Reference is made to U. S. Pat. No. 4,032,962 entitled "High Density Semiconductor integrated Circuit Layout" granted June 28, 1977 to J. Balyoz et al and of common assignee herewith.
Reference is made to U.S. Pat. No. 3,539,876 entitled "Monolithic Integrated Structure Including Fabrication Thereof" granted Nov. 10. 1970 to I. Feinberg et al and of common assignee herewith.
Reference is made to U.S. Pat. No. 3,633,268, entitled "Method of Producing One or More Large Integrated Semiconductor Circuits", granted Jan. 11, 1972 to R. Engbert.
As is apparent from the prior art, there are numerous semiconductor device fabrication techniques, and approaches known to the art for the fabrication of semiconductor devices. At least certain of these techniques have been or are employed in the art. Known approaches may for convenience be generally classified as "custom", and "masterslice". The interconnection metallurgy techniques, as known to the art, may be generally classified as "fixed", "discretionary" and "hybrid". Where "hybrid" is a wiring technique which at least in part combines the features of the "fixed" and "discretionary" techniques. Numerous wiring techniques, as generally classified supra have been employed in the art.